A Comprehensive Survey on RISC-V: From RISC-1 to RISC-5 Generations Through Modern Architecture, ISA Extensions, Customizable Core Designs, Comparative Analysis, and Real-World Applications

Abstract

RISC-V represents the pinnacle of open instruction set architecture (ISA) design, emerging from decades of RISC evolution at UC Berkeley. This comprehensive professional survey provides an in-depth examination of the RISC-V ecosystem spanning historical RISC-1 through RISC-5 pro- cessors (1981-2025), detailed ISA specifications with modern extensions (M, A, F, D, C, V, K), core generation classi- fications (E-Series embedded through P-Series datacenter), advanced customizable design frameworks (SiFive, Chipyard, Codasip), comprehensive architectural diagrams with proces- sor die photographs, detailed performance metrics, and real- world applications across IoT, automotive, aerospace, AI/ML, and high-performance computing sectors. As of 2025, RISC- V has achieved significant market penetration with revenues of $1.41 billion and projections reaching $17.4 billion by 2034 (37.85% CAGR). Major technology companies includ- ing SiFive, Western Digital, NVIDIA, Infineon, Qualcomm, and Alibaba have committed substantial resources to RISC- V development, with NVIDIA alone shipping over 1 billion RISC-V cores in 2024 and Infineon announcing production automotive processors with ISO 26262 certification.